In the field of radio communications and the field of clock signal generation, in order to achieve lower low in-band phase noise and high-frequency quantization noise, a clock signal frequency multiplication technology is required for reducing multiples of frequency multiplication of a phase-locked loop. The clock signal frequency multiplication technology may be implemented in a manner of an analog circuit and a digital circuit.
FIG. 1 shows a method of implementing clock signal frequency multiplication through a digital circuit. An exclusive-OR operation is performed on an input clock signal Vin and a clock signal obtained after the Vin being delayed by ΔT, to obtain a frequency multiplication output clock signal Vout. Generally, a duty cycle of an input clock signal is in a range of 40% to 60%. Implementing clock signal frequency multiplication through a digital circuit requires that the duty cycle of the input clock signal is close to 50% as much as possible, otherwise the output clock signal will include an additional spurious component. As shown in FIG. 2, the duty cycle of the input clock signal deviates from 50%. In this case, the output clock signal not only includes double frequency component of the input clock signal, but also includes single and triple frequency component. This deteriorates purity of the output clock signal of a phase-lock loop.
It can be learned from above that a difficulty of implementing clock signal frequency multiplication lies in calibration of a clock signal duty cycle. Using an analog circuit to implement calibration of a clock signal duty cycle is of relatively high power consumption and using a digital circuit to implement calibration of a clock signal duty cycle faces compromised restriction of a plurality of aspects such as phase noise, area, and dynamic range.